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Figure 1 from High Holding Current SCRs (HHI-SCR) for ESD protection

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Latch-up issue in CMOS Logic | Latch-up effect in VLSI - Team VLSI

Latch-Up Problem in CMOS – VLSI Design – Buzztech

[SOLVED] - How to use SCR as a Latch? | Forum for Electronics

Analog IC co-design for latch-up compliance - EDN Asia

What is Latch-Up and How to Test It - AnySilicon

Figure 1 from High Holding Current SCRs (HHI-SCR) for ESD protection

Latch-Up Problem in CMOS – VLSI Design – Buzztech

Earlier Is Better In Latch-Up Detection